View CS4220-KS_1028434.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com 24-bit stereo audio codec with 3v interface features l 100 db dynamic range a/d converters l 100 db dynamic range d/a converters l 105 db dac signal-to-noise ratio (eiaj) l analog volume control (cs4221 only) l differential inputs / outputs l on-chip anti-aliasing and output smoothing filters l de-emphasis for 32, 44.1 and 48 khz l supports master and slave modes l single +5 v power supply l on-chip crystal oscillator l 3 - 5 v digital interface description the cs4220/1 is a highly integrated, high performance, 24-bit, audio codec providing stereo analog-to-digital and stereo digital-to-analog converters using delta-sig- ma conversion techniques. the device operates from a single +5 v power supply, and features low power con- sumption. selectable de-emphasis filter for 32, 44.1, and 48 khz sample rates is also included. the cs4221 also includes an analog volume control ca- pable of 113.5 db attenuation in 0.5 db steps. the analog volume control architecture preserves dynamic range during attenuation. volume control changes are implemented using a soft ramping or zero crossing technique. applications include digital effects processors, dat, and multitrack recorders. ordering information CS4220-KS -10 to +70 c 28-pin ssop cs4221-ks -10 to +70 c 28-pin ssop cdb4220/1 evaluation board i scl/cclk sda/cdin ad0/cs mclk vd va rst lrck sclk sdin sdout dgnd agnd aoutl+ aoutl- aoutr+ aoutr- ainl- ainl+ ainr- ainr+ control port serial audio data interface digital filters with de-emphasis digital filters left dac right dac analog low pass and output stage voltage reference left adc right adc volume control ( dif1 )( dif0 )( dem0 ) ic/spi ( dem1 ) 2 clock osc ()=cs4220 volume control v l xti xto * =cs4221 * * apr 00 ds284pp3 cs4220 cs4221
cs4220 cs4221 2 ds284pp3 table of contents 1. characteristics and specifications ........................................................................ 4 analog characteristics ............................................................................................... 4 absolute maximum ratings .......................................................................................... 6 recommended operating conditions ...................................................................... 6 switching characteristics ......................................................................................... 7 switching characteristics - control port - spi mode (cs4221) .................... 8 switching characteristics - control port - i 2 c mode (cs4221) ..................... 9 2. typical connection diagram cs4220 ................................................................... 10 3. typical connection diagram cs4221 ................................................................... 11 4. register quick reference - cs4221 .......................................................................... 12 5. register descriptions - cs4221 .................................................................................. 13 5.1 adc control (address 01h) .............................................................................................. 13 5.1.1 power down adc (pdn) ....................................................................................... 13 5.1.2 left and right channel high pass filter defeat (hpdr-hpdl) ............................. 13 5.1.3 left and right channel adc muting (admr-adml) ............................................. 13 5.1.4 calibration control (cal) ....................................................................................... 13 5.1.5 calibration status (calp) (read only) .................................................................. 13 5.1.6 clocking error (clke) (read only) ....................................................................... 14 5.2 dac control (address 02h) .............................................................................................. 14 5.2.1 mute on consecutive zeros (mutc) ...................................................................... 14 5.2.2 mute control (mutr-mutl) .................................................................................. 14 5.2.3 soft ramp control (soft) .................................................................................... 14 5.2.4 soft ramp step rate (rmp) ................................................................................. 15 5.3 left channel output attenuator level (address 03h) ...................................................... 15 5.4 right channel output attenuator level (address 04h) ................................................... 15 5.4.1 attenuation level (att7-att0) ............................................................................... 15 5.5 dsp port mode (address 05h) ......................................................................................... 16 5.5.1 de-emphasis control (dem) .................................................................................. 16 5.5.2 serial input/output data sclk polarity select (dsck) ......................................... 16 5.5.3 serial data output format (dof) .......................................................................... 16 5.5.4 serial data input format (dif) ............................................................................... 16 5.6 converter status report (read only) (address 06h) ....................................................... 17 5.6.1 left and right channel acceptance bit (accr-accl) ......................................... 17 5.6.2 left and right channel adc output level (lvr and lvl) .................................... 17 5.7 master clock control (address 07h) ................................................................................ 17 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ i2c is a registered trademark of philips semiconductor. spi is a registered trademark of international business machines corporation. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and i s provided as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyr ights, trademarks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any mean s (electronic, mechanical, pho- tographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk m ay be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, i n any form or by any means (elec- tronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of ci rrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com.
cs4220 cs4221 ds284pp3 3 5.7.1 master clock control (mck) .................................................................................. 17 6. pin descriptions cs4220 ............................................................................................ 18 7. pin descriptions cs4221 ............................................................................................ 20 8. applications .............................................................................................................. ....... 22 8.1 overview .................................................................................................................. ........ 22 8.2 grounding and power supply decoupling ....................................................................... 22 8.3 high pass filter .......................................................................................................... ..... 22 8.4 analog outputs ............................................................................................................ .... 22 8.5 master vs. slave mode .................................................................................................... 2 2 8.6 de-emphasis ............................................................................................................... .... 22 8.7 power-up / reset / power down calibration ................................................................... 22 8.8 control port interface (cs4221 only) .............................................................................. 23 8.8.1 spi mode ............................................................................................................ 23 8.8.2 i 2 c mode ............................................................................................................. 23 8.9 memory address pointer (map) ...................................................................................... 24 8.9.1 auto-increment control (incr) .............................................................................. 24 8.9.2 register pointer (map) .......................................................................................... 24 9. adc/dac filter response ............................................................................................. 28 10. parameter definitions ................................................................................................ 29 11. package dimensions .................................................................................................... 30 list of figures figure 1. serial audio port data i/o timing .................................................................................. 7 figure 2. spi control port timing ............................................................................................ ..... 8 figure 3. i 2 c control port timing .................................................................................................. 9 figure 4. cs4220 recommended connection diagram ............................................................. 10 figure 5. cs4221 recommended connection diagram ............................................................. 11 figure 6. control port timing, spi mode .................................................................................... 24 figure 7. control port timing, i 2 c mode ..................................................................................... 24 figure 8. serial audio format 0 (i2s) ........................................................................................ .25 figure 9. serial audio format 1 .............................................................................................. .... 25 figure 10. serial audio format 2 ............................................................................................. ... 25 figure 11. serial audio format 3 ............................................................................................. ... 26 figure 12. optional input buffer ............................................................................................. ..... 26 figure 13. single-ended input application .................................................................................. 26 figure 14. 2- and 3-pole butterworth filters ............................................................................... 27 figure 15. hybrid digital/analog attenuation .............................................................................. 27 figure 16. de-emphasis curve ................................................................................................. .. 27 figure 17. hybrid analog/digital attenuation .............................................................................. 27 figure 18. adc filter response ............................................................................................... .. 28 figure 19. adc passband ripple ............................................................................................... 28 figure 20. adc transition band ............................................................................................... .. 28 figure 21. dac filter response ............................................................................................... .. 28 figure 22. dac passband ripple ............................................................................................... 28 figure 23. dac transition band ............................................................................................... .. 28 list of tables table 1. example volume settings ............................................................................................... 15 table 2. common clock frequencies........................................................................................... 18 table 3. digital interface format - dif1 and dif0 ....................................................................... 19 table 4. de-emphasis control ................................................................................................... ... 19 table 5. common clock frequencies........................................................................................... 20
cs4220 cs4221 4 ds284pp3 1. characteristics and specifications analog characteristics (t a = 25 c; va, vd = +5 v; full scale input sine wave, 997 hz; fs = 48 khz; measurement bandwidth is 20 hz to 20 khz; local components as shown in figures 4 and 5; spi a mode, format 0, unless otherwise specified.) notes: 1. referenced to typical full-scale differential input voltage (2 vrms). 2. filter characteristics scale with output sample rate. for output sample rates, fs, other than 48 khz, the 0.01 db passband edge is 0.4535x fs and the stopband edge is 0.625x fs. 3. the analog modulator samples the input at 6.144 mhz for an fs equal to 48 khz. there is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 mhz 21.8 khz where n = 0,1,2,3...). 4. group delay for fs = 48 khz, t gd = 15/48 khz = 312 s. parameter symbol cs4220/1 - ks unit min typ max analog input characteristics adc resolution - - 24 bits total harmonic distortion thd - 0.003 - % dynamic range a-weighted unweighted 95 92 100 97 - - db total harmonic distortion + noise (note 1) thd+n - -92 -87 db interchannel isolation (1 khz) - 90 - db interchannel gain mismatch - - 0.1 db offset error with high pass filter - - 0 lsb full scale input voltage (differential) 1.9 2.0 2.1 vrms gain drift - 100 - ppm/c input resistance 10 - - k w input capacitance - - 15 pf common mode input voltage - 2.3 - v a/d decimation filter characteristics passband (note 2) 0 - 21.8 khz passband ripple - - 0.01 db stopband (note 2) 30 - 6114 khz stopband attenuation (note 3) 80 - - db group delay (fs = output sample rate) (note 4) t gd -15/fs- s group delay variation vs. frequency d t gd --0s high pass filter characteristics frequency response -3 db (note 2) -0.1 db - - 3.7 20 - - hz phase deviation @ 20 hz (note 2) - 10 - degree passband ripple - - 0 db
cs4220 cs4221 ds284pp3 5 analog characteristics (continued) notes: 5. the passband and stopband edges scale with frequency. for input word rates, fs, other than 48 khz, the 0.01 db passband edge is 0.4535x fs and the stopband edge is 0.5465x fs. 6. digital filter characteristics. 7. measurement bandwidth is 10 hz to 3 fs. parameter symbol cs4220/1 - ks unit min typ max analog output characteristics - minimum attenuation, 10 k w , 100 pf load; unless otherwise specified. dac resolution - - 24 bits signal-to-noise, idle-channel noise (cs4221 only) dac muted, a-weighted 97 105 - db dynamic range dac not muted, a-weighted dac not muted, unweighted 95 92 100 97 - - db total harmonic distortion thd - 0.003 - % total harmonic distortion + noise thd+n - -92 -87 db interchannel isolation (1 khz) - 90 - db interchannel gain mismatch - - 0.1 db attenuation step size all outputs 0.35 0.5 0.65 db programmable output attenuation span 110 113.5 - db differential offset voltage - 10 - mv common mode output voltage - 2.4 - v full scale output voltage 1.8 1.9 2.0 vrms gain drift - 100 - ppm/ c out-of-band energy fs/2 to 2 fs - -60 - dbfs analog output load resistance capacitance 10 - - - - 100 k w pf combined digital and analog filter characteristics frequency response10 hz to 20 khz - 0.1 - db deviation from linear phase - 0.5 - degree passband: to 0.01 db corner (notes 5 and 6) 0 - 21.8 khz passband ripple (note 6) - - 0.01 db stopband (notes 5 and 6) 26.2 - - khz stopband attenuation (note 7) 70 - - db group delay (fs = input word rate) t gd -16/fs- s power supply power supply current va vd vl total power down - - - - 46 9 3 0.4 60 20 5 - ma power supply rejection ratio 1 khz - 65 - db
cs4220 cs4221 6 ds284pp3 digital characteristics (t a = 25 c; va, vd = 4.75v - 5.25v) absolute maximum ratings (agnd, dgnd = 0 v, all voltages with respect to 0 v.) recommended operating conditions (agnd, dgnd = 0 v, all voltages with respect to 0 v.) notes: 8. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 9. the maximum over or under voltage is limited by the input current. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min max unit high-level input voltage vl = 5v vl = 3v v ih v ih 2.8 2.0 vl + 0.3 vl + 0.3 v v low-level input voltage v il -0.3 0.8 v high-level output voltage at i o = -2.0 ma v oh vl - 1.0 - v low-level output voltage at i o = 2.0 ma v ol -0.5v input leakage current digital inputs - 10 a output leakage current high impedance digital outputs - 10 a parameter symbol min max unit power supplies digital analog vd va -0.3 -0.3 6.0 6.0 v input current (note 8) - 10 ma analog input voltage (note 9) -0.7 va + 0.7 v digital input voltage (note 9) -0.7 vd + 0.7 v ambient temperature power applied -55 +125 c storage temperature -65 +150 c parameter symbol min typ max unit power supplies digital analog digital | va - vd | vd va vl 4.75 4.75 2.7 - 5.0 5.0 5.0 - 5.25 5.25 5.25 0.4 v ambient operating temperature t a -10 25 70 c
cs4220 cs4221 ds284pp3 7 switching characteristics (t a = 25 c; va, vd = 4.75 v - 5.25 v; outputs loaded with 30 pf) notes: 10. after powering up the cs4220/1, pdn should be held low for 10 ms to allow the power supply to settle. parameter symbol min typ max unit audio adcs and dacs sample rate fs 4 - 50 khz xti frequency xti = 256, 384, or 512 fs 1.024 - 26 mhz xti pulse width high xti = 512 fs xti = 384 fs xti = 256 fs 13 21 31 - - - - - - ns xti pulse width low xti = 512 fs xti = 384 fs xti = 256 fs 13 21 31 - - - - - - ns xti jitter tolerance - 500 - psrms rst low time (note 10) 10 - - ms sclk falling edge to sdout output valid dsck = 0 t dpd -- ns lrck edge to msb valid t lrpd - - 45 ns sdin setup time before sclk rising edge dsck = 0 t ds 25 - - ns sdin hold time after sclk rising edge dsck = 0 t dh 25 - - ns sclk period t sckw --ns sclk high time t sckh 40 - - ns sclk low time t sckl 40 - - ns sclk rising to lrck edge dsck = 0 t lrckd 35 - - ns lrck edge to sclk rising dsck = 0 t lrcks 40 - - ns 1 (384) fs --------------------- -20 + 1 (128) fs --------------------- - sckh sckl sckw t t t msb msb-1 *sclk shown for dsck = 0, sclk inverted for dsck = 1. t dpd sdout lrck sclk* sdin dh t ds t lrpd t lrcks t lrckd t figure 1. serial audio port data i/o timing
cs4220 cs4221 8 ds284pp3 switching characteristics - control port - spi mode (cs4221) (t a = 25 c; va, vd = 4.75 v - 5.25 v; inputs: logic 0 = dgnd, logic 1 = vd; c l = 30 pf) notes: 11. not tested but guaranteed by design. 12. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 13. data must be held for sufficient time to bridge the transition time of cclk. 14. for f sck < 1 mhz. parameter symbol min max unit spi mode (spi /i2c = 0) cclk clock frequency f sck -6mhz rst rising edge to cs falling (note 11) t srs 41 - s cclk edge to cs falling (note 12) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 13) t dh 15 - ns rise time of cclk and cdin (note 14) t r2 -100ns fall time of cclk and cdin (note 14) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 2. spi control port timing
cs4220 cs4221 ds284pp3 9 switching characteristics - control port - i 2 c mode (cs4221) (t a = 25 c; va, vd = 4.75 v - 5.25 v; inputs: logic 0 = dgnd, logic 1 = vd; c l = 30 pf) notes: 15. not tested but guaranteed by design. 16. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i 2 c ? mode (spi /i2c = 1) scl clock frequency f scl -100khz rst rising edge to start (note 15) t irs 50 - s bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time for scl falling (note 16) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl t rc -25ns fall time of scl t fc -25ns rise time of sda t rd -1s fall time of sda t fd -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t rc t fc t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst t rd t fd figure 3. i 2 c control port timing
cs4220 cs4221 10 ds284pp3 2. typical connection diagram cs4220 ainl+ ainl- 1 f + 0.1 f 2 w 0.1 f + 1f +5v supply 21 6 va vd ferrite bead 2.2 nf 150 w 150 w ainr+ ainr- 2.2 nf 150 w 150 w 20 19 17 16 22 7 agnd dgnd 10 11 mode selection dif1 dif0 5 4 audio dsp sclk lrck 9 sdin 8 sdout r s r s cs4220 27 rst r=500 w nc 1 nc 14 nc 15 nc 28 r s r s s 0.1 f + 1f 13 vl +2.7 - 5v 47 k w * * required for master mode only digital audio source 18 25 26 aoutl+ aoutl- 24 23 analog filter aoutr+ aoutr- 12 dem0 dem1 xti xto 2 3 external clock input 40 pf 40 pf eliminate the crystal and capacitors when using an external clock input analog filter figure 4. cs4220 recommended connection diagram (also see recommended layout diagram )
cs4220 cs4221 ds284pp3 11 3. typical connection diagram cs4221 ainl+ ainl- 1 f + 0.1 f 2 w 0.1 f + 1f +5v supply 21 6 va vd ferrite bead 2.2 nf 150 w 150 w ainr+ ainr- 2.2 nf 150 w 150 w 20 19 17 16 22 7 agnd dgnd 12 27 microcontroller ad0/cs rst cs4221 18 i2c/spi r = 500 w nc 1 nc 14 nc 15 nc 28 s 0.1 f + 1f +2.7 - 5v 10 11 scl/cclk sda/cdin * required for master mode only 4 5 audio dsp sclk lrck 9 sdin 8 sdout r s r s r s r s 13 vl * 47 k w 25 26 aoutl+ aoutl- 24 23 analog filter aoutr+ aoutr- xti xto 2 3 external clock input 40 pf 40 pf eliminate the crystal and capacitors when using an external clock input analog filter figure 5. cs4221 recommended connection diagram (also see recommended layout diagram )
cs4220 cs4221 12 ds284pp3 4. register quick reference - cs4221 addr function 7 6 5 4 3 2 1 0 0h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 1h adc control pdn hpdr hpdl admr adml cal calp clke default 0 0 0 0 0 0 0 0 2h dac control reserved mutc mutr mutl soft reserved rmp1 rmp0 default 0 0 0 0 0 0 0 0 3h-4h output attenuator level att7 att6 att5 att4 att3 att2 att1 att0 default 0 0 0 0 0 0 0 0 5h dsp port mode reserved dem1 dem0 dsck dof1 dof0 dif1 dif0 default 0 0 0 0 0 0 0 0 6h converter status report accr accl lvr2 lvr1 lvr0 lvl2 lvl1 lvl0 default 0 0 0 0 0 0 0 0 7h master clock con- trol reserved reserved reserved reserved reserved reserved mck1 mck0 default 0 0 0 0 0 0 0 0
cs4220 cs4221 ds284pp3 13 5. register descriptions - cs4221 note: all registers are read/write in i 2 c mode and write-only in spi mode, unless otherwise noted. 5.1 adc control (address 01h) 5.1.1 power down adc (pdn) default = 0 0 - disabled 1 - enabled function: the adc will enter a low-power state when this function is enabled. 5.1.2 left and right channel high pass filter defeat (hpdr-hpdl) default = 0 0 - disabled 1 - enabled function: the internal high-pass filter is defeated when this function is enabled. control of the internal high- pass filter is independent for the left and right channel. 5.1.3 left and right channel adc muting (admr-adml) default = 0 0 - disabled 1 - enabled function: the output for the selected adc channel will be muted when this function is enabled. 5.1.4 calibration control (cal) default = 0 0 - disabled 1 - enabled function: the device will automatically perform an offset calibration when brought out of reset, which last ap- proximately 50 ms. when this function is enabled, a rising edge on the reset line will initiate an offset calibration. 5.1.5 calibration status (calp) (read only) default = 0 0 - calibration done 1 - calibration in progress 76543210 pdn hpdr hpdl admr adml cal calp clke 00000000
cs4220 cs4221 14 ds284pp3 5.1.6 clocking error (clke) (read only) default = 0 0 - no error 1 - error 5.2 dac control (address 02h) 5.2.1 mute on consecutive zeros (mutc) default = 0 0 - disabled 1 - enabled function: the dac output will mute following the reception of 512 consecutive audio samples of static 0 or -1 when this function is enabled. a single sample of non-static data will release the mute. detection and muting is done independently for each channel. the muting function is affected, similar to volume control changes, by the soft bit in the dac control register. 5.2.2 mute control (mutr-mutl) default = 0 0 - disabled 1 - enabled function: the output for the selected dac channel will be muted when this function is enabled. the muting function is affected, similar to volume control changes, by the soft bit in the dac control register. 5.2.3 soft ramp control (soft) default = 0 0 - soft ramp level changes 1 - zero cross level changes function: soft ramp level changes will be implemented by incrementally ramping, in 0.5 db steps, from the cur- rent level to the new level. the rate of change defaults to 0.5 db per 8 left/right clock periods and is adjustable through the rmp bits in the dac control register. zero cross level changes will be implemented in a single step from the current level to the new level. the level change takes effect on a zero crossing to minimize audible artifacts. if the signal does not encounter a zero crossing, the level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 khz sample rate). zero crossing is independently monitored and implemented for each channel. the accr and accl bits in the converter status report register indicate when a level change has occurred for the right and left channel. 76543210 reserved mutc mutr mutl soft reserved rmp1 rmp0 00000000
cs4220 cs4221 ds284pp3 15 5.2.4 soft ramp step rate (rmp) default = 00 00 - 1 step per 8 lrck's 01 - 1 step per 4 lrck's 10 - 1 step per 16 lrck's 11 - 1 step per 32 lrck's function: the rate of change for the soft ramp function is adjustable through the rmp bits. 5.3 left channel output attenuator level (address 03h) 5.4 right channel output attenuator level (address 04h) 5.4.1 attenuation level (att7-att0) default = 00h function: the output attenuator level registers allow for attenuation of the dac outputs in 0.5 db increments from 0 to 113.5 db. level changes are implemented with an analog volume control until the residual output noise is equal to the noise floor in the mute state. at this point, volume changes are performed digitally. this technique is superior to purely digital volume control because the noise is attenuated by the same amount as the signal, thus preserving dynamic range, see figure 16. volume changes are performed as dictated by the soft bit in the dac control register. att0 represents 0.5 db of attenuation and settings greater than 227 (decimal value) will mute the selected dac output. 76543210 att7 att6 att5 att4 att3 att2 att1 att0 00000000 binary code decimal value volume setting 00000000 0 0 db 11100011 227 -113.5 db 11100100 228 muted table 1. example volume settings
cs4220 cs4221 16 ds284pp3 5.5 dsp port mode (address 05h) 5.5.1 de-emphasis control (dem) default = 00 00 - 44.1 khz de-emphasis setting 01 - 48 khz de-emphasis setting 10 - 32 khz de-emphasis setting 11 - de-emphasis disabled function: selects the appropriate digital filter to maintain the standard 15 m s/50 m s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates, see figure 15. 5.5.2 serial input/output data sclk polarity select (dsck) default = 0 0 - data valid on rising edge of sclk 1 - data valid on falling edge of sclk function: this function selects the polarity of the sclk edge used to clock data in and out of the serial audio port. 5.5.3 serial data output format (dof) default = 00 00 - i 2 s compatible 01 - left justified 10 - right justified, 24-bit 11 - right justified, 20-bit function: the required relationship between the left/right clock, serial clock and output serial data is defined by the serial data output format, and the options are detailed in figures 8-11. note: if the format selected is right-justified, sclk must be 64 fs when operating in slave mode. 5.5.4 serial data input format (dif) default = 00 00 - i 2 s compatible 01 - left justified 10 - right justified, 24-bit 11- right justified, 20-bit function: the required relationship between the left/right clock, serial clock and input serial data is defined by the serial data input format, and the options are detailed in figures 8-11. 76543210 reserved dem1 dem0 dsck dof1 dof0 dif1 dif0 00000000
cs4220 cs4221 ds284pp3 17 5.6 converter status report (read only) (address 06h) 5.6.1 left and right channel acceptance bit (accr-accl) default = 0 0 - requested setting valid 1 - new setting loaded function: the accr and accl bits indicate when a change in the output attenuator level has occurred for the left and right channels, respectively. the value will be high when a new setting is loaded into the output attenuator level registers. the value will return low when the requested attenuation setting has taken effect. 5.6.2 left and right channel adc output level (lvr and lvl) default = 000 000 - normal output levels 001 - -6 db level 010 - -5 db level 011 - -4 db level 100 - -3 db level 101 - -2 db level 110 - -1 db level 111 - clipping function: the analog-to-digital converter is continually monitoring the peak digital signal output for both the left and right channel, prior to the digital limiter. the maximum output value is stored in the lvl and lvr bits. the lvl and lvr bits are sticky, so they are reset after each read is performed. 5.7 master clock control (address 07h) 5.7.1 master clock control (mck) default = 00 00 - xti = 256 fs for master mode 01 - xti = 384 fs for master mode 10 - xti = 512 fs for master mode function: the mck bits allow for control of the master clock, xti, input frequency. note: these bits are not valid when operating in slave mode. 76543210 accr accl lvr2 lvr1 lvr0 lvl2 lvl2 lvl0 00000000 76543210 reserved reserved reserved reserved reserved reserved mck1 mck0 00000000
cs4220 cs4221 18 ds284pp3 6. pin descriptions cs4220 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 nc rst aoutl- aoutl+ aoutr+ aoutr- agnd va sdout dgnd vd sclk lrck xti xto nc 9 10 11 12 17 18 19 20 ainl+ ainl- dem1 ainr+ dem0 dif0 dif1 sdin 13 14 15 16 ainr- nc nc vl cs4220 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 nc rst aoutl- aoutl+ aoutr+ aoutr- agnd va sdout dgnd vd sclk lrck xti xto nc 9 10 11 12 17 18 19 20 ainl+ ainl- dem1 ainr+ dem0 dif0 dif1 sdin 13 14 15 16 ainr- nc nc vl cs4220 nc 1,14,15, 28 no connect - these pins are not connected internally and should be tied to dgnd to mini- mize noise coupling. xti, xto 2,3 crystal connections ( input/output ) - input and output connections for the crystal used to clock the cs4220. alternatively, a clock may be input into xti. this is the clock source for the delta-sigma modulator and digital filters. the frequency of this clock must be either 256x, 384x, or 512x fs in slave mode and 256x in master mode. lrck 4 left/right clock ( input ) - determines which channel is currently being input/output of the serial audio data pins sdin/sdout. the frequency of the left/right clock must be equal to the input sample rate. although the outputs for each adc channel are transmitted at different times, left/right pairs represent simultaneously sampled analog inputs. the required relation- ship between the left/right clock, serial clock and serial data is defined by the dif1-0 pins. the options are detailed in figures 8 - 11. sclk 5 serial data clock ( input ) - clocks the individual bits of the serial data into the sdin pin and out of the sdout pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dif1-0 pins. the options are detailed in figures 8 - 11. vd 6 digital power ( input ) - positive power supply for the digital section. typically 5.0 vdc. dgnd 7 digital ground ( input ) - digital ground for the digital section. sdout 8 serial data output ( output ) - two's complement msb-first serial data is output on this pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dif1-0 pins. the options are detailed in figures 8 - 11. sdin 9 serial data input ( input ) - two's complement msb-first serial data is input on this pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dif1-0 pins. the options are detailed in figures 8 - 11. fs (khz) xti (mhz) 256x 384x 512x 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 table 2. common clock frequencies
cs4220 cs4221 ds284pp3 19 dif0, dif1 10,11 digital interface format ( input ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format. the options are detailed in fig- ures 8 - 11. dem0, dem1 12,18 de-emphasis select ( input ) - controls the activation of the standard 50/15 s de-emphasis filter. 32, 44.1, or 48 khz sample rate selection defined in table 4. vl 13 digital logic power ( input ) - positive power supply for the digital interface section. typically 3.0 to 5.0 vdc. ainr-, ainr+ 16,17 differential right channel analog input ( input ) - the full scale analog input level (differen- tial) is specified in the analog characteristics specification table and may be ac coupled or dc coupled into the device, see figure 12 for optional line input buffer. ainl-, ainl+ 19,20 differential left channel analog input ( input ) - the full scale analog input level (differential) is specified in the analog characteristics specification table and may be ac coupled or dc coupled into the device, see figure 12 for optional line input buffer. va 21 analog power ( input ) - positive power supply for the analog section. nominally +5 volts. agnd 22 analog ground ( input ) - analog ground reference. aoutr-, aoutr+ 23, 24 differential right channel analog output ( output ) - the full scale analog output level (dif- ferential) is specified in the analog characteristics specification table. aoutl-, aoutl+ 25, 26 differential left channel analog output ( output ) - the full scale analog output level (differ- ential) is specified in the analog characteristics specification table. rst 27 reset ( input ) - when low, the device enters a low power mode and all internal registers are reset, including the control port. when high, the control port becomes operational and normal operation will occur. dif1 dif0 description format figure 00 i 2 s, up to 24-bit data 08 0 1 left justified, up to 24-bit data 1 9 1 0 right justified, 24-bit data 2 10 1 1 right justified, 20-bit data 3 11 table 3. digital interface format - dif1 and dif0 dem0 dem1 de-emphasis 0 0 32 khz 0 1 44.1 khz 1 0 48 khz 1 1 disabled table 4. de-emphasis control
cs4220 cs4221 20 ds284pp3 7. pin descriptions cs4221 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 nc rst aoutl- aoutl+ aoutr+ aoutr- agnd va sdout dgnd vd sclk lrck xti xto nc 9 10 11 12 17 18 19 20 ainl+ ainl- i2c/spi ainr+ ad0/cs sda/cdin scl/cclk sdin 13 14 15 16 ainr- nc nc vl cs4221 nc 1,14,15, 28 no connect - these pins are not connected internally and should be tied to dgnd to mini- mize noise coupling. xti, xto 2,3 crystal connections ( input/output ) - input and output connections for the crystal used to clock the cs4221. alternatively a clock may be input into xti. this is the clock source for the delta-sigma modulator and digital filters. the frequency of this clock must be either 256x, 384x, or 512x fs. the default xti setting in master mode is 256x, but this may be changed to 384x or 512x through the control port. lrck 4 left/right clock ( input ) - determines which channel is currently being input/output of the serial audio data pins sdin/sdout. the frequency of the left/right clock must be equal to the input sample rate. although the outputs for each adc channel are transmitted at different times, left/right pairs represent simultaneously sampled analog inputs. the required relation- ship between the left/right clock, serial clock and serial data is defined by the dsp port mode (05h) register. the options are detailed in figures 8 - 11. sclk 5 serial data clock ( input ) - clocks the individual bits of the serial data into the sdin pin and out of the sdout pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dsp port mode (05h) register. the options are detailed in figures 8 - 11. vd 6 digital power ( input ) - positive power supply for the digital section. typically 5.0 vdc. dgnd 7 digital ground ( input ) - digital ground for the digital section. sdout 8 serial data output ( output ) - two's complement msb-first serial data is output on this pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dsp port mode (05h) register. the options are detailed in figures 8 - 11. fs (khz) xti (mhz) 256x 384x 512x 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 table 5. common clock frequencies
cs4220 cs4221 ds284pp3 21 sdin 9 serial data input ( input ) - two's complement msb-first serial data is input on this pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dsp port mode (05h) register. the options are detailed in figures 8 - 11. scl/cclk 10 serial control port clock ( input ) - clocks the serial control bits into and out of the cs4221. in i 2 c mode, scl requires an external pull-up resistor according to the i 2 c specification. sda/cdin 11 serial control port data ( input/output )- sda is a data i/o line in i 2 c mode and requires an external pull-up resistor according to the i 2 c specification. cdin in the input data line for the serial control port in spi mode. ad0/cs 12 address bit/control chip select ( input ) - in i 2 c mode, ad0 is a chip address bit. in spi mode, cs is used to enable the control port interface on the cs4221. the cs4221 control port interface is defined by the spi /i2c pin. vl 13 logic power ( input ) - positive power supply for the digital interface section. typically 3.0 to 5.0 vdc. ainr-, ainr+ 16,17 differential right channel analog input ( input ) - the full scale analog input level (differen- tial) is specified in the analog characteristics specification table and may be ac coupled or dc coupled into the device, see figure 12 for optional line input buffer. i2c/spi 18 control port format ( input ) - when this pin is high, i 2 c mode is selected, when low, spi is selected. ainl-, ainl+ 19,20 differential left channel analog input ( input ) - the full scale analog input level (differential) is specified in the analog characteristics specification table and may be ac coupled or dc coupled into the device, see figure 12 for optional line input buffer. va 21 analog power ( input ) - positive power supply for the analog section. typically 5.0 vdc. agnd 22 analog ground ( input ) - analog ground reference. aoutr-, aoutr+ 23, 24 differential right channel analog outputs ( output ) - the full scale analog output level (dif- ferential) is specified in the analog characteristics specification table. aoutl-, aoutl+ 25, 26 differential left channel analog outputs ( output ) - the full scale analog output level (dif- ferential) is specified in the analog characteristics specification table. rst 27 reset ( input ) - when low, the device enters a low power mode and all internal registers are reset, including the control port. when high, the control port becomes operational and normal operation will occur.
cs4220 cs4221 22 ds284pp3 8. applications 8.1 overview the cs4220 is a stand-alone device controlled through dedicated pins. the cs4221 is controlled with an external microcontroller using the serial control port. 8.2 grounding and power supply decoupling as with any high resolution converter, the cs4220/1 requires careful attention to power sup- ply and grounding arrangements to optimize per- formance. figures 4 and 5 shows the recommended power arrangement with va, vd and vl connected to clean supplies. decoupling capacitors should be located as close to the device package as possible. if desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin. 8.3 high pass filter the operational amplifiers in the input circuitry driving the cs4220/1 may generate a small dc off- set into the a/d converter. the cs4220/1 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc lev- el, possibly yielding "clicks" when switching be- tween devices in a multichannel system. 8.4 analog outputs the recommended off-chip analog filter is either a 2nd order butterworth or a 3rd order butterworth, if greater out-of-band noise filtering is desired. the cs4220/1 dac interpolation filter has been pre- compensated for an external 2nd order butterworth filter with a 3 db corner at fs, or a 3rd order but- terworth filter with a 3 db corner at 0.75 fs to pro- vide a flat frequency response and linear phase over the passband (see figure 14 for fs = 48 khz). if the recommended filter is not used, small frequency re- sponse magnitude and phase errors will occur. in addition to providing out-of-band noise attenua- tion, the output filters shown in figure 14 provide differential to single-ended conversion. 8.5 master vs. slave mode the cs4220/1 may be operated in either master mode or slave mode. in master mode, sclk and lrck are outputs which are internally derived from mclk. the device will operate in master mode when a 47 k w pulldown resistor is present on sdout at startup or after reset, see figure 5. lrck and sclk are inputs to the cs4220/1 when operating in slave mode. see figures 8-11 for the available clocking modes. 8.6 de-emphasis the cs4220/1 includes digital de-emphasis for 32, 44.1, or 48 khz sample rates. the frequency re- sponse of the de-emphasis curve, as shown in fig- ure 15, will scale proportionally with changes in samples rate, fs. the de-emphasis feature is in- cluded to accommodate older audio recordings that utilize pre-emphasis as a means of noise reduction. de-emphasis control is achieved with the dem1/0 pins on the cs4220 or through the dem1-0 bits in the dsp port mode byte (#5) on the cs4221. 8.7 power-up / reset / power down calibration upon power up, the user should hold rst = 0 for approximately 10 ms. in this state, the control port is reset to its default settings and the part remains in the power down mode. at the end of rst , the de- vice performs an offset calibration which lasts ap- proximately 50 ms after which the device enters normal operation. in the cs4221, a calibration may also be initiated via the cal bit in the adc con- trol byte (#1). the calp bit in the adc control byte is a read only bit indicating the status of the calibration. reset/power down is achieved by lowering the rst pin causing the part to enter power down.
cs4220 cs4221 ds284pp3 23 once rst goes high, the control port is functional and the desired settings should be loaded. the cs4220/1 will also enter power down mode if the master clock source stops for approximately 10 s or if the lrck is not synchronous to the master clock. the control port will retain its current settings. the cs4220/1 will mute the analog outputs and en- ter the power down mode if the supply drops below approximately 4 volts. 8.8 control port interface (cs4221 only) the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi a and i 2 c a , with the cs4221 operating as a slave device. the con- trol port interface format is selected by the spi /i2c pin. 8.8.1 spi mode in spi mode, cs is the cs4221 chip select signal, cclk is the control port bit clock, cdin is the in- put data line from the microcontroller and the chip address is 0010000. all signals are inputs and data is clocked in on the rising edge of cclk. figure 6 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which must be low to write. regis- ter reading from the cs4221 is not supported in the spi mode. the next 8 bits form the memory ad- dress pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into a register desig- nated by the map. the cs4221 has a map auto increment capability, enabled by the incr bit in the map register. if incr is a zero, then the map will stay constant for successive writes. if incr is set to a 1, then map will auto increment after each byte is written, al- lowing block writes of successive registers. regis- ter reading from the cs4221 is not supported in the spi mode. 8.8.2 i 2 c mode in i 2 c mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 7. there is no cs pin. pin ad0 forms the partial chip address and should be tied to vd or dgnd as desired. the upper 6 bits of the 7 bit ad- dress field must be 001000. in order to communi- cate with the cs4221, the lsb of the chip address field (first byte sent to the cs4221) should match the setting of the ad0 pin. the eighth bit of the ad- dress byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer which selects the reg- ister to be read or written. if the operation is a read, the contents of the register pointed to by the mem- ory address pointer will be output. setting the auto increment bit in map, allows successive reads or writes of consecutive registers. each byte is sepa- rated by an acknowledge bit.
cs4220 cs4221 24 ds284pp3 8.9 memory address pointer (map) 8.9.1 auto-increment control (incr) default = 0 0 - disabled 1 - enabled 8.9.2 register pointer (map) default = 000 76543210 incr reserved reserved reserved reserved map2 map1 map0 00000000 cs cclk cdin chip address 0010000 r/w map data msb lsb byte 1 byte n map = memory address pointer figure 6. control port timing, spi mode sda scl 001000 addr ad0 r/w ack data 1-8 ack data 1-8 ack start stop figure 7. control port timing, i 2 c mode
cs4220 cs4221 ds284pp3 25 master slave i 2 s, up to 24-bit data xti = 256, 384, 512 fs (cs4223 - 256 fs only) lrck = 4 to 50 khz sclk = 64 fs i 2 s, up to 24-bit data xti = 256, 384, 512 fs lrck = 4 to 50 khz sclk = 48,64, 128 fs lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 8. serial audio format 0 (i 2 s) figure 9. serial audio format 1 master slave left-justified, up to 24-bit data xti = 256, 384, 512 fs (cs4223 - 256 fs only) lrck = 4 to 50 khz sclk = 64 fs left-justified, up to 24-bit data xti = 256, 384, 512 fs lrck = 4 to 50 khz sclk = 48, 64, 128 fs lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 10. serial audio format 2 master slave right-justified, 24-bit data xti = 256, 384, 512 fs (cs4223 - 256 fs only) lrck = 4 to 50 khz sclk = 64 fs right-justified, 24-bit data xti = 256, 384, 512 fs lrck = 4 to 50 khz sclk = 64 fs lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel
cs4220 cs4221 26 ds284pp3 figure 11. serial audio format 3 master slave right-justified, 20-bit data xti = 256, 384, 512 fs (cs4223 - 256 fs only) lrck = 4 to 50 khz sclk = 64 fs right-justified, 20-bit data xti = 256, 384, 512 fs lrck = 4 to 50 khz sclk = 64 fs lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 12. optional input buffer input 10 f + 150 w 2.2 nf 4.7 f + 0.1 f ainr- ainr+ cs4223/4 figure 13. single-ended input application
cs4220 cs4221 ds284pp3 27 figure 14. 2- and 3-pole butterworth filters gain db -10 db 0 db frequency t2 = 15 s t1 = 50 s f1 f2 figure 15. de-emphasis curve signal noise 0 0 -113.5 attenuation (db) amplitude (db) analog digital figure 16. hybrid analog/digital attenuation
cs4220 cs4221 28 ds284pp3 9. adc/dac filter response figure 17. adc filter response figure 18. adc passband ripple figure 19. adc transition band figure 20. dac filter response figure 21. dac passband ripple figure 22. dac transition band
cs4220 cs4221 ds284pp3 29 10. parameter definitions dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 hz to 20 khz), including distortion components. expressed in decibels. adcs are measured at -1 dbfs as suggested in aes17-1991 annex a and dacs are measured at 0 dbfs. idle channel noise / signal-to-noise-ratio the ratio of the rms analog output level with 1 khz full scale digital input to the rms analog output level with all zeros into the digital input. measured a-weighted over a 10 hz to 20 khz bandwidth. units in deci- bels. this specification has been standardized by the audio engineering society, aes17-1991, and re- ferred to as idle channel noise. this specification has also been standardized by the electronic industries association of japan, eiaj cp-307, and referred to as signal-to-noise-ratio. total harmonic distortion (thd) thd is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. units in decibels. interchannel isolation a measure of crosstalk between channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. frequency response a measure of the amplitude response variation from 20 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel gain mismatch for the adcs, the difference in input voltage that generates the full scale code for each channel. for the dacs, the difference in output voltages for each channel with a full scale digital input. units are in deci- bels. gain error the deviation from the nominal full scale output for a full scale input. gain drift the change in gain value with temperature. units in ppm/c. offset error for the adcs, the deviation in lsb's of the output from mid-scale with the selected inputs tied to a com- mon potential. for the dac's, the differential output voltage with mid-scale input code. units are in volts.
cs4220 cs4221 30 ds284pp3 11. package dimensions notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.15 0.25 a2 0.064 0.069 0.074 1.62 1.75 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.390 0.4015 0.413 9.90 10.20 10.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.0354 0.041 0.63 0.90 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimension is millimeters 28l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
? notes ?

▲Up To Search▲

Price & Availability of CS4220-KS

	To Download CS4220-KS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .